1. Field of the Invention
The present invention relates to trace or via-programmable, usually metal programmable, read only memories (ROMs), and more particularly to space-efficient layouts for ROMs of this type.
2. State of the Art
Read only memories are widely used in computers and electronic devices of various descriptions. Frequently, a ROM is incorporated within an Application Specific Integrated Circuit (ASIC). A ROM of a given capacity and word size is typically understood to require a given amount of space on an integrated circuit. Referring to FIG. 1 for example, in the case of a conventional metal-programmable parallel ROM architecture, transistors are connected in pairs to a working potential VSS and to a bitline. Each transistor stores a single bit of information. The existence of a conducting path between VSS and the bitline or the lack of such a conducting path determines for a given transistor whether a logic zero or a logic one is programmed. For every two bits of information, there is one VSS line. In a typical 0.35 .mu.m process, the pitch of two transistors in series and the metal pitch are the same. The resulting overhead (lost space) due to VSS connections is therefore calculated as 1/(2+1)=33%.
The capacity and word size of a ROM are design requirements for a particular ASIC design, thereby fixing the amount of space required for the ROM. However, there may arise a need to accommodate additional circuitry on an ASIC including a ROM without increasing the die size of the ASIC. If the ROM could be compacted, or laid out more efficiently, then space on the integrated circuit would then be freed up for other circuitry for the same die cost (area). In other instances, compacting of the ROM may allow for a smaller die size and a more economical package to be used.